>> The next (obvious) question: What's gonna happen w/ Xilinx.
Altera will have a process advantage over Xilinx and there is nothing that can be done about it. While everyone is talking 14nm, Intel is shipping it and talking 10nm.
This deal makes more sense than any I've seen. Altera gets to use the best fabs in the world to gain an advantage over their competitors. Intel gets to deploy to a new (to them) market where the volumes are lower but the ASPs are higher - this is good given the ever increasing costs of making chips and the lower yields likely at 10nm and 7nm. It looks like a purely strategic move for both companies.
I'd be curious to see just how long it will take Altera to adopt such a fine process for FPGA cells though.
Edit: ha! Apparently, "One reason why Altera is attractive to Intel is that Altera is already using Intel's fab to create its latest generation FPGAs and SoCs; Arria 10 FPGAs and SoCs are being implemented using TSMC's 20nm process, while Stratix 10 FPGAs and SoCs are leveraging Intel’s 14 nm Tri-Gate process (see Altera & Intel to Collaborate on Multi-Die 14nm FPGAs). Furthermore, Altera is also using Intel's state-of-the-art packaging technologies."
I believe the Xilinx tools are actually free of cost. Still, though, open source FPGA tools are desperately needed.
edit: even if they just opened up the bitfile format. I believe it's a similar situation as GPU instructions sets though: managers saying "no because patents".
I recently wrote a place and route tool for Lattice iCE40 FPGAs [0]. The bitstream was reverse engineered by Clifford Wolf and others as part of the IceStorm project [1]. We're using Yosys [2] for Verilog synthesis, also written by Clifford.
Wow, that is pretty awesome. I didn't expect this to have arrived that quickly.
Does it support user constraints on relative placement (and routing)? Self-timed logic, such as NULL Convention Logic [1], doesn't fit well with the synchronous FPGA paradigm, but can be implement on those if the feedback loops are tightly controlled [2]. I'd like to play with that :)
Whoa, I had no idea you could do async circuits on an FPGA (although I can't get to [2] right now, the site is under maintenance). Right now, I only support IO constraints. The IceStorm project hasn't documented the timing model yet but it is in pipeline. Is it possible to do what you want with vendor tools? Anyways, email me and we can chat about what you'd need.
Xilinx tools are only free for certain chips and feature sets. If you want tools like ChipScope (which more than pays for itself) or to use any Vertex chips you need to buy their software.
For their lower end chips (All the Spartan series, the larger of the 6 series are still quite useful) they straight up announced an end of development on the main toolchain (ISE) with no plans for support on their newer one.
Opening up the spec alone is not ideal, and its not just for the patents. Hardware validation of a software spec is expensive. Today they don't need to do that. They can simply change the software to work around broken hardware and nobody needs to know.
I hope the same, but it's not likely in the short term. Intel seems to understand open better than a lot of hardware companies, but it's still got its share of NDAs. And a proprietary compiler AFAIK.
I don't understand the logic there. No FPGA vendor will ever turn a profit on their EDA-ware, and nobody would ever buy an FPGA without it. Open the stuff up and let people do some of the heavy lifting. They can still sell value-added bits and bobs if the want, and can concentrate on usability, something they sorely need to do.
In business - "the hard part" == "competitive advantage" . If you open source that , soon you'll see more competitors knocking on your doors.
For example, if intel wanted, it could have built a decent FPGA, probably in a reasonable time(there were startups that built decent fpga's).
But building good fpga software ? that it couldn't do, first because it's really hard and second because you need tens of thousands of designs from your customers to run on this in ordered to make good software. That's not something acquirable.
But whatever level of advantage they have here now is negated by xilinxes existence of a toolset with roughly that level of engineering effort. So why not, in the least, consider damaging the only true competition by opening up?
If we look at WebKit, And OpenCV and i think OpenGL , the software is really a complement to the real business and are less hard to develop than the main products.Also they are all in the API business - where developers demand open source and have enough power .
As for android - Again it was a strategic necessity for Google, since it needed that distribution point for it's huge ad business. Operating systems are a winner takes all business and the most effective, lowest risk strategy to get there was open sourcing, even though it's kind of a loss leader. And even with only partially open-sourcing android , Google is at constant risk of losing control of android.
The situation in FPGA is different - if altera opens the tool, xilinx and other companies will probably use it , and we'll probably see multiple companies compete on the business.
Right, I understand. Logic synthesis entails constraint solving and other big domain-specific challenges. It is a very difficult problem. (So are web rendering, OS development, graphics API design, and computer vision.)
While this is obviously a win for Altera: they gain the Intel process advantage; this deal does have a number of advantages for Xilinx:
- Altera will now likely lose early access to all the non-Intel fabs. And sometimes one of the non-Intel fabs come up with a process advantage before Intel does. Fabs love to work with FPGA vendors: the regular structure makes them good targets for new processes; and FPGA vendors are the only people that can sell a single chip for $50,000.
- Big guys are only interested in big markets: Altera may abandon some of the smaller niches they currently play in.
I'm sure there are other advantages Xilinx gains by staying independent.
>> Fabs love to work with FPGA vendors: the regular structure makes them good targets for new processes
I heard that this has changed and mobile chips are being used for "pipe cleaning" in fabs, from a credible source, but i haven't dug into the details of how.
I'm thinking it could be interesting for Nvidia, considering that they have been building up HPC as their second leg, as an insurance policy in case Intel invests heavily into tooling and process technology for FPGA. Plus they're in a partnership with IBM now, who probably have some interesting use cases for future FPGAs (i.e. deep learning).
Basically, they're fucked. Altera's next chip was going to wipe the floor with Xilinx anyways. Xilinx has better tools, but they are going to be in trouble now that they are behind in process.
They'll get acquired by someone, probably in a year or two. If they lose their market leadership in the meantime, the acquisition will be for less than 17B.
They really need to invest in their software and tool flow right now. That's where they have a strong lead.
For the longest time, the FPGA market has been dominated by Xilinx and Altera. With one joining Intel, it seems logical to expect a response?